1. Field of the Invention
The present invention relates to a memory interface control circuit and memory interface control method for reading data from a memory. More specifically, the present invention relates to a memory interface control circuit and memory interface control method for reading data from a double data rate 2-synchronous random access memory (hereinafter, “DDR2-SDRAM”).
2. Description of the Related Art
DDR-SDRAM has experienced substantial growth over the past several years. The DDR-SDRAM is a synchronous dynamic random access memory (“synchronous DRAM” or “SDRAM”) having a high-rate data transfer function called “double data rate (“DDR”) mode”. In the DDR mode, data can be read and written at both rising and falling of a clock signal which is provided for synchronizing respective circuits in a computer.
The DDR-SDRM inputs and outputs data at a frequency twice as high as that of an external clock, so that a width of definitely set data is smaller than that for a single data rate SDRAM (“SDR SDRAM”). If the wiring lengths from the memory (DDR SDRM) to a controller are different, time required until data reaches to a receiver (flight time) is also different, thereby, it is difficult to determine a timing at which the receiver accepts data. The DDR-SDRAM adopts a data strobe signal (“DQS”) to notify the receiver of a data transfer timing. The DQS is a bidirectional strobe signal and functions as a data input and output operation reference clock in both read and write operations.
As shown in FIG. 1, in the read operation, an edge of the DQS coincides with an edge of read data. In the write operation, the edge of the DQS is located at the center of write data. If the controller receives the read data from the DDR-SDRAM, the received DQS is delayed and shifted to the center of the read data within the DDR-SDRAM.
The DQS in a read cycle will next be described.
In the read cycle, the DDR-SDRAM controls the DQS synchronized with a clock (CLK). The receiver accepts data (DQ) based on the DQS. The DQS operates in the read cycle as follows.    (1) While data (DQ) is not output, the DQS is in a high impedance state (indicated by “201” in FIG. 3.    (2) After a read command (READ) is input, the DQS turns into a low level about one clock before the data DQ is output (indicated by “202” in FIG. 3).    (3) When effective data starts to be output from the memory, the DQS starts to toggle at the same frequency as that of the CLK and continues to toggle until burst read is finished (indicated by “203” in FIG. 3). In the example of FIG. 3, effective data in the form of burst data corresponding to two time slots (Q0 and Q1) are present, and the DQS toggles twice, accordingly.    (4) When the burst read is finished, the DQS returns to the high impedance state.
As shown in FIG. 2, a data strobe pattern in the read operation consists of a preamble state, a toggle state, and a postamble state.
If the DDR-SDRAM receives the read command (READ) in a bank active state, the DQS changes from the high impedance state to a low level. This low level corresponds to a read preamble state. The read preamble state appears about one clock before first data is output. Following the read preamble state, the DQS toggles at the same frequency as that of the clock CLK while m data has effective data on a data input and output terminal (DQ). After last data is transferred, a low-level period corresponding to a read postamble state starts. The read postamble state continues for a time of about a half clock since an edge of the last data appears.
The DQS changes from the high impedance state to the preamble state, and changes from the postamble state to the high impedance state. In a transition period from the postamble state to the high impedance state, a glitch noise is generated due to signal reflection.
An operation of a conventional DDR-SDRAM interface will be described with reference to FIG. 4. In the conventional DDR-SDRM, the glitch noise causes destruction of data in a first-in first-out (FIFO) buffer serving as an output buffer. However, since a transfer frequency is lower than an LSI-side clock CLK, synchronization can be still established.
Prior art literatures relating to the present invention are as follows: JPA 2001-189078, JPA 2003-050739, JPA 2003-059267 and JPA 2003-173290.
As a next-generation memory to the DDR-SDRAM, a double data rate 2-synchronous random access memory (“DDR2-SDRAM”) has appeared.
The DDR2-SDRAM differs from the DDR-SDRAM in the following respects. A package of DDR2-SDRAM is FBGA, while that of the DDR-SDRAM is TSOP. A power supply voltage of DDR2-SDRAM is 1.8 volts, while that of the DDR-SDRAM is 2.5 volts. A maximum capacity of DDR2-SDRAM is 2 gigabytes (Gbyte), while that of the DDR-SDRAM is 1 Gbyte. The number of internal banks of DDR2-SDRAM is 4 or 8, while that of the DDR-SDRAM is 4. An operating speed of DDR2-SDRAM is twice as high as that of the DDR-SDRAM. A signal terminating end of DDR2-SDRAM is a chip while that of the DDR-SDRAM is a mother board.
Since the transfer frequency of the DDR2-SDRAM is twice as high as that of the DDR-SDRAM, synchronization cannot be established without processing data as shown in FIG. 5. Thus, each wiring length is set so that data can be transferred satisfactorily even if a glitch noise is superimposed on the data, and placement of a plurality of RAMs is restricted. Even if the mask is set at a specific timing to prevent the glitch noise from being superimposed on the DQS, the placement of a plurality of RAMs are still restricted.
The conventionally used DDR-SDRAM has a low transfer frequency. Due to this, as shown in FIG. 4, even if the glitch noise is superimposed on the data while the data is changed to the high impedance state, a window for accepting data is still present. However, since the transfer frequency of the DDR2-SDRM is twice as high as that of the DDR-SDRAM, the window for synchronizing data, as shown in FIG. 5, is not present.